FIG. 1 (prior art) shows a block diagram of a basic memory component 100, which includes a control interface 102 and a collection of four logical banks B0-B3 distributed among four quadrants 104. Each logical bank includes left and right sub-banks: for example, bank B0 includes a left sub-bank LB0 in the upper left quadrant and a right sub-bank RB0 in the lower right quadrant 104. As discussed in more detail below, physically separating banks reduces local power-supply fluctuations resulting from memory accesses, and consequently reduces deleterious noise and the resultant adverse impact on speed performance.
Each quadrant 104 includes a two-dimensional array of storage cells (not shown), a row/column address decoder 105, and sense amplifiers 106. Decoders 105 activate specified rows and access columns of the memory cells, while sense amplifiers 106 sense and temporarily store data extracted from a specified row in the associated banks or sub-banks. Data moved to or from the storage cells through a sense amplifier by an “activate” operation are available for access by read and write operations. Data is delivered to and extracted from memory component 100 via respective write pipes 107 and read pipes 108.
A “column” is the quanta of data accessed in a given row currently residing in the sense amplifier during a read or write operation. An external device, typically a memory controller, accesses the storage cells in one logical bank (e.g., sub-banks LB0 and RB0) by issuing an appropriate data-access request (read request or write request) to control interface 102, which in turn presents the appropriate address and control signals to the specified sub-banks via internal address and control buses 110.
FIG. 2A (prior art) illustrates the movement of data during three steps for accessing data in one of the logical banks introduced in FIG. 1. Step one is an activate operation in which data from a selected row in each of a corresponding pair of sub-banks are selected and placed into the associated sense amplifiers. Step two is a data-access (read or write) operation in which one column of the selected row (held in the sense amplifiers) is selected and accessed. Data from the sense amplifiers are transferred to read pipes 108 (read data), or data in write pipes 107 is transferred into the sense amplifiers. In FIG. 2A, the label “c” means “column.”
Step three is a precharge operation. The sub-banks and sense amplifiers are deselected and left in a state in which another activate operation can access a different row. Prior to deselection, the data in the sense amplifiers, including any data modified by a write operation, are copied back to the storage cells of the selected row of the selected logical bank. In the present disclosure, an “operation” refers to memory operations, for example, one of the above mentioned steps (activate, read, write, precharge). A “transaction” specifies a sequence of one or more operations that accesses a memory component. The following examples assume that transactions are directed to precharged banks and that each transaction performs a precharge operation after each read or write operation.
FIG. 2B (prior art) is a timing diagram illustrating a read transaction directed to a precharged logical bank. A clock signal CLK is shown across the top of the diagram for reference. The “RQ” label identifies a collection of control/address signals that convey transaction requests to control interface 102, the label “DATA” identifies information conveyed to an external requestor, and the label “READ” identifies data conveyed to read pipes 108. The illustrative read transaction includes the following events:                1. At clock edge 0, interface 102 receives an ACT (activate) command specifying one row of a logical bank, logical bank B0 in this example. Via control buses 110, control interface 102 asserts a bit-sense signal BSen to specified logical bank B0, and thus opens one corresponding row in each sub-bank LB0 and RB0. Opening the rows requires power, and thus produces a power spike 210 on supply voltage Vdd. As shown in FIG. 1, each quadrant 104 is connected locally to supply voltage Vdd, and sub-banks are physically separated. The physical separation reduces the combined impact of accessing the sub-banks, but each quadrant 104 nevertheless suffers some supply-voltage degradation.        2. At clock edge 5, control interface 102 receives a read command RD for a given column of the now active logical bank B0. Control interface 102 responds by issuing a column-selection signal CSel via buses 110 to selected sub-columns within the selected sub-banks LB0 and RB0. Column accesses are power intensive, and thus produce another power spike 215. In this example, the column access causes 32 bits of read data RD from each sub-bank of the selected logical bank to be conveyed to read pipes 108. The two 32-bit data words from the read pipes together make up a single 64-bit data word DQ.        3. At clock edge 9, control interface 102 receives a PRE (precharge) command for the logical bank B0. Control interface 102 responds by issuing a precharge signal Pre via buses 110 to sub-banks LB0 and RB0 to deselect the logical banks in preparation for subsequent read and write transactions. The precharge operation once again draws supply power, and consequently produces yet another power spike 220. (The shapes and sizes of spikes 210, 215, and 220 are merely illustrative.)Write transactions, similar to read transactions and producing similar power spikes, are well understood and are therefore omitted here for brevity.        
Power-supply spikes of the type described above limit device performance. As noted above, the amplitude of such spikes is limited by dividing memory banks into widely separated sub-banks. Other approaches include the use of more and wider power buses and increased local bypass capacitance. Unfortunately, these approaches consume die area, and are thus undesirable.